Xilinx Virtex-5 FPGA ML561 Uživatelský manuál

RVirtex-5 FPGA ML561Memory InterfacesDevelopment BoardUser GuideUG199 (v1.2.1) June 15, 2009

10 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Preface: About This GuideRHardware MeasurementsThese measurements are the

100 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRFPGA #2 PinoutTable A-2 lists the connections fo

Virtex-5 FPGA ML561 User Guide www.xilinx.com 101UG199 (v1.2.1) June 15, 2009FPGA #2 PinoutRDDR2 DIMM Deep Interface (cont.)DDR2_DIMM3_CK2_P AA25 DDR2

102 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRDDR2 DIMM Deep Interface (cont.)DDR2_DIMM_DQ_BY4

Virtex-5 FPGA ML561 User Guide www.xilinx.com 103UG199 (v1.2.1) June 15, 2009FPGA #2 PinoutRDDR2 DIMM Wide Interface (cont.)DDR2_DIMM5_CS0_N V24 DDR2_

104 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRDDR2 DIMM Wide Interface (cont.)DDR2_DIMM_DQ_BY1

Virtex-5 FPGA ML561 User Guide www.xilinx.com 105UG199 (v1.2.1) June 15, 2009FPGA #2 PinoutRDDR2 DIMM Miscellaneous Signals (cont.)DDR2_DIMM5_CNTL_PAR

106 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRFPGA #2 Test and Debug SignalsFPGA2_DIP0 AG18 FP

Virtex-5 FPGA ML561 User Guide www.xilinx.com 107UG199 (v1.2.1) June 15, 2009FPGA #2 PinoutRFPGA #2 External Interfaces (cont.)FPGA2_TXN0_BK120 B3 FPG

108 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRFPGA #3 PinoutTable A-3 lists the connections fo

Virtex-5 FPGA ML561 User Guide www.xilinx.com 109UG199 (v1.2.1) June 15, 2009FPGA #3 PinoutRQDRII Memory Interface (cont.) QDR2_D_BY0_B5 M31 QDR2_D_BY

Virtex-5 FPGA ML561 User Guide www.xilinx.com 11UG199 (v1.2.1) June 15, 2009RChapter 1IntroductionThis chapter introduces the Virtex®-5 FPGA ML561 ref

110 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRQDRII Memory Interface (cont.) QDR2_D_BY7_B6 U28

Virtex-5 FPGA ML561 User Guide www.xilinx.com 111UG199 (v1.2.1) June 15, 2009FPGA #3 PinoutRQDRII Memory Interface (cont.) QDR2_Q_BY6_B7 V33 QDR2_Q_BY

112 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRRLDRAM II Memory Interface (cont.)RLD2_D_BY0_B5

Virtex-5 FPGA ML561 User Guide www.xilinx.com 113UG199 (v1.2.1) June 15, 2009FPGA #3 PinoutRRLDRAM II Memory Interface (cont.)RLD2_DQ_BY3_B4 M7 RLD2_D

114 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRFPGA #3 Test and Debug Signals (cont.)FPGA3_TEST

Virtex-5 FPGA ML561 User Guide www.xilinx.com 115UG199 (v1.2.1) June 15, 2009RAppendix BBill of MaterialsThis appendix lists the bill of materials (BO

116 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix B: Bill of MaterialsRPower15A Power Module Texas Instruments PTH

Virtex-5 FPGA ML561 User Guide www.xilinx.com 117UG199 (v1.2.1) June 15, 2009RSwitchDIP (Test Inputs) ITT_INDUSTRIES SDA04H1KDSW1, SW2, SW6System Rese

118 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix B: Bill of MaterialsR

Virtex-5 FPGA ML561 User Guide www.xilinx.com 119UG199 (v1.2.1) June 15, 2009RAppendix CLCD InterfaceThis appendix describes the LCD interface for the

12 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 1: IntroductionRVirtex-5 FPGA ML561 Memory Interfaces Development

120 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRTable C-1 summarizes the controller specificati

Virtex-5 FPGA ML561 User Guide www.xilinx.com 121UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRPeripheral Device KS0713Figure C-2 is a block

122 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRFigure C-3 shows only the signals of interest f

Virtex-5 FPGA ML561 User Guide www.xilinx.com 123UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRController – OperationThe pixels for the LCD p

124 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceR0010DB0Page 210HDB111HDB212HDB313HDB414HDB515HD

Virtex-5 FPGA ML561 User Guide www.xilinx.com 125UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRWhen a page is addressed, all the bits represe

126 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRController – Power Supply CircuitsFigure C-5 sh

Virtex-5 FPGA ML561 User Guide www.xilinx.com 127UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRThe voltage and contrast settings must be conf

128 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceR• The voltage follower and voltage regulator ar

Virtex-5 FPGA ML561 User Guide www.xilinx.com 129UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRAfter the SHL bit is configured, these setting

Virtex-5 FPGA ML561 User Guide www.xilinx.com 13UG199 (v1.2.1) June 15, 2009Virtex-5 FPGA ML561 Memory Interfaces Development BoardRFigure 1-2 shows t

130 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRInstruction SetTable C-6 shows the instruction

Virtex-5 FPGA ML561 User Guide www.xilinx.com 131UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRSet page address 0 0 1 0 1 1 P3 P2 P1 P0This i

132 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRReverse display ON/OFF001010011REVREV RAM bit d

Virtex-5 FPGA ML561 User Guide www.xilinx.com 133UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRRead/Write Characteristics (6800 Mode)Table C-

134 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRDesign ExamplesLCD Panel Used in Full Graphics

Virtex-5 FPGA ML561 User Guide www.xilinx.com 135UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRLCD Panel Used in Character ModeThis design ex

136 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRDisplay Data ByteThe supplied byte must be a va

Virtex-5 FPGA ML561 User Guide www.xilinx.com 137UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRWhen presenting byte value 30 hex, character 0

138 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceRFigure C-11 shows a block diagram of the LCD ch

Virtex-5 FPGA ML561 User Guide www.xilinx.com 139UG199 (v1.2.1) June 15, 2009Hardware Schematic DiagramRArray Connector NumberingFigure C-12 shows the

14 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 1: IntroductionR

140 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix C: LCD InterfaceR

Virtex-5 FPGA ML561 User Guide www.xilinx.com 15UG199 (v1.2.1) June 15, 2009RChapter 2Getting StartedThis chapter describes the items needed to config

16 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 2: Getting StartedR5. Insert the CompactFlash card included in the

Virtex-5 FPGA ML561 User Guide www.xilinx.com 17UG199 (v1.2.1) June 15, 2009RChapter 3Hardware DescriptionThis chapter describes the major hardware bl

18 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRFPGAThe ML561 uses three Virtex-5 XC5VLX50

Virtex-5 FPGA ML561 User Guide www.xilinx.com 19UG199 (v1.2.1) June 15, 2009Hardware OverviewRMemoriesTable 3-1 lists the types of memories that the M

Virtex-5 FPGA ML561 User Guide www.xilinx.com UG199 (v1.2.1) June 15, 2009Xilinx is disclosing this user guide, manual, release note, and/or specifica

20 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRDDR2 SDRAM ComponentsThe ML561 board conta

Virtex-5 FPGA ML561 User Guide www.xilinx.com 21UG199 (v1.2.1) June 15, 2009Memory DetailsRMemory DetailsDDR400 and DDR2 Component MemoriesThe FPGA #1

22 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRTable 3-3 describes all signals associated

Virtex-5 FPGA ML561 User Guide www.xilinx.com 23UG199 (v1.2.1) June 15, 2009Memory DetailsRDDR2 SDRAM DIMMThe FPGA #2 device on the Virtex-5 FPGA ML56

24 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRTable 3-5 describes all the signals associ

Virtex-5 FPGA ML561 User Guide www.xilinx.com 25UG199 (v1.2.1) June 15, 2009Memory DetailsRQDRII and RLDRAM II MemoriesFigure 3-5 summarizes the distr

26 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRTable 3-6 describes all the signals associ

Virtex-5 FPGA ML561 User Guide www.xilinx.com 27UG199 (v1.2.1) June 15, 2009External InterfacesRExternal InterfacesThe external interfaces of the Virt

28 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionR200 MHz LVPECL ClockThe 200 MHz LVPECL clo

Virtex-5 FPGA ML561 User Guide www.xilinx.com 29UG199 (v1.2.1) June 15, 2009External InterfacesR33 MHz System ACE Controller OscillatorA single-ended

Virtex-5 FPGA ML561 User Guide www.xilinx.com 3UG199 (v1.2.1) June 15, 2009Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . .

30 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRSeven-Segment DisplaysOne seven-segment di

Virtex-5 FPGA ML561 User Guide www.xilinx.com 31UG199 (v1.2.1) June 15, 2009External InterfacesRPower On or Off Slide SwitchThe power on or off slide

32 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRLiquid Crystal Display ConnectorPrevious m

Virtex-5 FPGA ML561 User Guide www.xilinx.com 33UG199 (v1.2.1) June 15, 2009Power RegulationRThe product specification at http://www.displaytech.com.h

34 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRalso be supplied from a bench supply using

Virtex-5 FPGA ML561 User Guide www.xilinx.com 35UG199 (v1.2.1) June 15, 2009Power RegulationRThe FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_

36 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRTable 3-18 summarizes the inhibit headers.

Virtex-5 FPGA ML561 User Guide www.xilinx.com 37UG199 (v1.2.1) June 15, 2009Board Design ConsiderationsRFor Write data and terminations at the memory,

38 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 3: Hardware DescriptionRTable 3-19 shows the details of the dielec

Virtex-5 FPGA ML561 User Guide www.xilinx.com 39UG199 (v1.2.1) June 15, 2009RChapter 4Electrical RequirementsThis chapter provides the electrical requ

4 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009RSeven-Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . .

40 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 4: Electrical RequirementsRTable 4-1: ML561 Power ConsumptionDevic

Virtex-5 FPGA ML561 User Guide www.xilinx.com 41UG199 (v1.2.1) June 15, 2009Power ConsumptionRPower Modules CapacityVCCINT Power Plane (1.0V) 1 1.00 1

42 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 4: Electrical RequirementsRTable 4-2 lists the 12 different power

Virtex-5 FPGA ML561 User Guide www.xilinx.com 43UG199 (v1.2.1) June 15, 2009Power ConsumptionRcurrent can support a voltage swing of up to (16 mA * 50

44 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 4: Electrical RequirementsRSSTL18 FPGA Power Plane (1.8V) Capacity

Virtex-5 FPGA ML561 User Guide www.xilinx.com 45UG199 (v1.2.1) June 15, 2009Power ConsumptionRSystem ACE Controller1 3.3 200 0.7DS080, System ACE Comp

46 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 4: Electrical RequirementsRFPGA Internal Power BudgetTable 4-4 sum

Virtex-5 FPGA ML561 User Guide www.xilinx.com 47UG199 (v1.2.1) June 15, 2009RChapter 5Signal Integrity RecommendationsTermination and Transmission Lin

48 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 5: Signal Integrity RecommendationsRTable 5-1: DDR400 SDRAM Compon

Virtex-5 FPGA ML561 User Guide www.xilinx.com 49UG199 (v1.2.1) June 15, 2009Termination and Transmission Line SummariesRTable 5-4: QDRII SRAM Terminat

Virtex-5 FPGA ML561 User Guide www.xilinx.com 5UG199 (v1.2.1) June 15, 2009RAppendix B: Bill of MaterialsAppendix C: LCD InterfaceGeneral . . . . .

50 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 5: Signal Integrity RecommendationsR

Virtex-5 FPGA ML561 User Guide www.xilinx.com 51UG199 (v1.2.1) June 15, 2009RChapter 6ConfigurationThis chapter provides a brief description of the FP

52 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 6: ConfigurationRJTAG ChainFour devices (the System ACE chip and t

Virtex-5 FPGA ML561 User Guide www.xilinx.com 53UG199 (v1.2.1) June 15, 2009System ACE InterfaceRTable 6-2 shows the System ACE interface signal names

54 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 6: ConfigurationR

Virtex-5 FPGA ML561 User Guide www.xilinx.com 55UG199 (v1.2.1) June 15, 2009RChapter 7ML561 Hardware-Simulation CorrelationThis chapter contains the f

56 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRillustrated here for thes

Virtex-5 FPGA ML561 User Guide www.xilinx.com 57UG199 (v1.2.1) June 15, 2009Test SetupRstrobe, a random value can be applied to data bits from one cyc

58 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationR♦ DDR2 mask (for nominal

Virtex-5 FPGA ML561 User Guide www.xilinx.com 59UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRDDR2 Component Write OperationThis su

6 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009R

60 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRDDR2 DQ is a bidirectiona

Virtex-5 FPGA ML561 User Guide www.xilinx.com 61UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-4: DDR2 Component Write HW M

62 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-6: DDR2 Componen

Virtex-5 FPGA ML561 User Guide www.xilinx.com 63UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-8: DDR2 Component Write Extr

64 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-10: DDR2 Compone

Virtex-5 FPGA ML561 User Guide www.xilinx.com 65UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRDDR2 Component Read OperationThis sub

66 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-13: DDR2 Compone

Virtex-5 FPGA ML561 User Guide www.xilinx.com 67UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-15: DDR2 Component Read HW M

68 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-17: DDR2 Compone

Virtex-5 FPGA ML561 User Guide www.xilinx.com 69UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-19: DDR2 Component Read Extr

Virtex-5 FPGA ML561 User Guide www.xilinx.com 7UG199 (v1.2.1) June 15, 2009RPrefaceAbout This GuideThis user guide describes the Virtex®-5 FPGA ML561

70 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRDDR2 DIMM Write Operation

Virtex-5 FPGA ML561 User Guide www.xilinx.com 71UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRDDR2 DQ is a bidirectional signal. To

72 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-22: DDR2 DIMM Wr

Virtex-5 FPGA ML561 User Guide www.xilinx.com 73UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-24: DDR2 DIMM Write HW Measu

74 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-26: DDR2 DIMM Wr

Virtex-5 FPGA ML561 User Guide www.xilinx.com 75UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-28: DDR2 DIMM Write Extrapol

76 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRDDR2 DIMM Read OperationT

Virtex-5 FPGA ML561 User Guide www.xilinx.com 77UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-31: DDR2 DIMM Read HW Measur

78 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-33: DDR2 DIMM Re

Virtex-5 FPGA ML561 User Guide www.xilinx.com 79UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-35: DDR2 DIMM Read Extrapola

8 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Preface: About This GuideR- Configurable Logic Blocks (CLBs)-SelectIO™ Reso

80 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-37: DDR2 DIMM Re

Virtex-5 FPGA ML561 User Guide www.xilinx.com 81UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRQDRII Write OperationThis subsection

82 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-40: QDRII Write

Virtex-5 FPGA ML561 User Guide www.xilinx.com 83UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-42: QDRII Write HW Measureme

84 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-44: QDRII Write

Virtex-5 FPGA ML561 User Guide www.xilinx.com 85UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-46: QDRII Write Extrapolatio

86 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRQDRII Read OperationThis

Virtex-5 FPGA ML561 User Guide www.xilinx.com 87UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-49: QDRII Read HW Measuremen

88 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-51: QDRII Read H

Virtex-5 FPGA ML561 User Guide www.xilinx.com 89UG199 (v1.2.1) June 15, 2009Signal Integrity Correlation ResultsRFigure 7-53: QDRII Read Extrapolation

Virtex-5 FPGA ML561 User Guide www.xilinx.com 9UG199 (v1.2.1) June 15, 2009ConventionsRConventionsThis document uses the following conventions. An exa

90 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRFigure 7-55: QDRII Read E

Virtex-5 FPGA ML561 User Guide www.xilinx.com 91UG199 (v1.2.1) June 15, 2009Summary and RecommendationsRSummary and RecommendationsThe first objective

92 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationRTable 7-16 summarizes the

Virtex-5 FPGA ML561 User Guide www.xilinx.com 93UG199 (v1.2.1) June 15, 2009How to Generate a User-Specific FPGA IBIS ModelRHow to Generate a User-Spe

94 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation CorrelationR

Virtex-5 FPGA ML561 User Guide www.xilinx.com 95UG199 (v1.2.1) June 15, 2009RAppendix AFPGA PinoutsThis appendix provides the pinouts for the three FP

96 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRDDR400 Component Interface (cont.)DDR1_DQ_BY0_B4

Virtex-5 FPGA ML561 User Guide www.xilinx.com 97UG199 (v1.2.1) June 15, 2009FPGA #1 PinoutRDDR2 Component Interface (cont.)DDR2_WE_N J21 DDR2_DQ_BY2_B

98 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Appendix A: FPGA PinoutsRFPGA #1 MII Link InterfaceFPGA2_TO_FPGA1_MII_TX_C

Virtex-5 FPGA ML561 User Guide www.xilinx.com 99UG199 (v1.2.1) June 15, 2009FPGA #1 PinoutRFPGA #1 Test Display SignalsFPGA1_7SEG_0_N AG17 FPGA1_7SEG_