Xilinx LOGICORE UG144 Uživatelský manuál stáhnout pdf (Strana 111)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 111

UG144 April 24, 2009

Multiple Cores

-- DISCONTINUED PRODUCT --

Note:

Although not illustrated, if the optional Management Interface is used, host_clk can also be

shared between cores.

With RGMII

Figure 10-4 illustrates sharing clock resources across multiple instantiations of the core

using the optional RGMII. gtx_clk may be shared between multiple cores as illustrated,

resulting in a common transmitter clock domain across the device.

As a general rule, a common receiver clock domain is not possible. Each core receives an

independent receiver clock from the PHY attached to the other end of the RGMII—as

illustrated in Figure 10-4. This results in a separate receiver clock domain for each core.

Note:

Although not illustrated, if the optional Management Interface is used, host_clk can also be

shared between cores.

Figure 10-3: Clock Management Logic with External GMII (Multiple Cores)

IBUFG

BUFG

gtx_clk

gmii_rx_clk1

1-Gigabit Ethernet MAC

gmii_rx_clkgtx_clk

IBUFG

BUFG

IBUFG

BUFG

gmii_rx_clk2

1-Gigabit Ethernet MAC

gmii_rx_clkgtx_clk

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Xilinx LOGICORE UG144 Uživatelský manuál Strana 111