Xilinx V2.1 Uživatelský manuál

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Printed in U.S.A.
Xilinx System
Generator v2.1
for
Simulink
User Guide
Xilinx Blockset
Reference Guide
Introduction
Xilinx Blockset Overview
Xilinx Blocks
System Generator Software Features
Using the Xilinx Software
Auxiliary Files
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Strany 1 - Generator v2.1

— Printed in U.S.A.Xilinx SystemGenerator v2.1forSimulinkUser GuideXilinx BlocksetReference GuideIntroductionXilinx Blockset OverviewXilinx BlocksSys

Strany 2 - About This Manual

10 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide3 and simply use floating point operations in hardware. The answer is that most

Strany 3 - Additional Resources

100 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe block parameters dialog box can be invoked by double-clicking the icon in

Strany 4 - Conventions

MATLAB I/O 101Xilinx BlocksNET "Dout<2>" FAST;NET "Dout_valid" FAST;• Specify IOB Location Constraints: Checking this optio

Strany 5 - Contents

102 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideMemoryThis section contains Xilinx blocks that use Xilinx memory LogiCOREs.Du

Strany 6

Memory 103Xilinx Blocksby the port’s address input. During a write cycle, the user can configure the behaviorof the data out ports A/B to one of the fo

Strany 7 - Chapter 6 Auxiliary Files

104 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideVirtex, Virtex-E and Spartan-II families support only Read After Write. Virte

Strany 8 - Introduction

Memory 105Xilinx BlocksXilinx LogiCOREThe block uses the Xilinx LogiCORE: Dual Port Block Memory v3.2 The addresswidth must be equal towhere d denotes

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106 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideFIFOThe Xilinx FIFO block implements a First-In-First-Out memoryqueue.Values

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Memory 107Xilinx Blocks• Store Only Valid Data: when checked, the block will not store any invaliddata words; i.e., when the din sample is invalid, th

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108 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by

Strany 12 - Arithmetic Data Types

Memory 109Xilinx BlocksOther parameters usedby thisblock areexplained in the CommonParameters sectionof the previous chapter.Xilinx LogiCOREThe block

Strany 13 - Hardware Handshaking

The System Generator Design Flow 11IntroductionThe System Generator design flow is shown in the following figure.Figure 1-1: System Generator design fl

Strany 14

110 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidebetween 16 to 4096, inclusive for the other FPGA families. The word width mus

Strany 15 - Xilinx Blockset Overview

Memory 111Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model.Fig

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112 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• Read After Write• Read Before Write• No Read On WriteThe write modes can be

Strany 17 - Port Data Types

Memory 113Xilinx BlocksXilinx LogiCOREThe block always uses a Xilinx LogiCORE Single Port Block Memory V3.2 orDistributed Memory V5.0. For the block m

Strany 18 - Licensed Cores

114 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\doc\sp_block_mem.

Strany 19 - Versions

State Machine 115Xilinx Blocksstream of bits. The state transition diagram and equivalent transition table are shownbelow.Figure 3-77: Mealy State M

Strany 20 - Generate Core

116 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe rows of the matrices correspond to the current state, and columns corresp

Strany 21 - Override with Doubles

State Machine 117Xilinx BlocksA block diagram of this type of state machine is shown below:Figure 3-80: Moore State Machine block diagramThe block i

Strany 22 - Sample Period

118 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe Next State Matrix and the and Output Array are composed in the following

Strany 23 - Xilinx Blocks

State Machine 119Xilinx BlocksXilinx LogiCOREThis block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE andVersion 5.0 of the Xilinx

Strany 24

12 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideSimulink hierarchy into a hierarchical VHDL netlist. In addition, System Gene

Strany 25

120 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidestream of bits. The state transition diagram and equivalent transition table

Strany 26 - Addressable Shift Register

State Machine 121Xilinx BlocksThe Registered Mealy State Machine block is configured with next state and outputmatrices obtained from the next state/ou

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122 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe number of bits used to implement a registered mealy state machine is give

Strany 28 - Black Box

State Machine 123Xilinx BlocksRegistered Moore State MachineThe Xilinx Registered MooreState Machine blockimplementsa state machine whose output depen

Strany 29

124 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidestream of bits. The state transition diagram and next state/output table are

Strany 30 - Block Interface

State Machine 125Xilinx BlocksThe Next State Matrix and the Output Array are composed in the following way:Figure 3-90: Construction of Next State a

Strany 31 - Constant

126 Xilinx Development SystemXilinx System Generator v2.1 Reference GuidewhereNs = total number of next state logic block RAM bitsk =ds= depth of stat

Strany 32

Using the System Generator installer 127System Generator Software FeaturesChapter 4System Generator Software FeaturesThis chapter briefly describes how

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128 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideInstalled System Generator directoryThe installer will create the following d

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Using Black Boxes 129System Generator Software FeaturesNote - For this example to run correctly, you must change your directory (cd withinthe MATLAB c

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Hardware Handshaking 13IntroductionGenerator then propagates signal types and precisions as appropriate. Theautomatically chosen type is the least ex

Strany 36 - Down Sample

130 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideUse of mixed language projectsSystem Generator v2.1 supports mixed language (

Strany 37 - Get Valid Bit

Use of mixed language projects 131System Generator Software Featuresenter information describing clocks, parameter names, types and values asappropria

Strany 38

132 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidevlog<file>line for each Verilog wrapper that is listed in the verilogFi

Strany 39 - Parallel to Serial

Using the System Generator Constraints Files 133System Generator Software Featuresenable or clear port may result in large fanout signals, thus degrad

Strany 40 - Register

134 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe division of the design into parts, and the speed at which each part must

Strany 41

Using the System Generator Constraints Files 135System Generator Software FeaturesThe ce2_group contains the blocksoperating at twice the system perio

Strany 42 - Reinterpret

136 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidecell array of strings in the box labeled IOB Pad Locations. Locations are pa

Strany 43 - Serial to Parallel

Files automatically created by System Generator 137System Generator Software FeaturesFiles automatically created by System GeneratorWhen aSystem Gener

Strany 44

138 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• sysgen.log - log file.• xlRunScripts.log - log file showing status of post-pr

Strany 45 - Set Valid Bit

Xilinx ISE 4.1i Project Navigator 139Using the Xilinx SoftwareChapter 5Using the Xilinx SoftwareThis chapter describes how to process your System Gene

Strany 46

14 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBit-True and Cycle-True ModelingSystem Generator produces a hardware implement

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140 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideNavigator properties dialog. Right-click on the device and default package at

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Xilinx ISE 4.1i Project Navigator 141Using the Xilinx SoftwareIn the Sources window, select the top-level VHDL module in your design. Now youwill not

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142 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• pn_posttranslate.do - this file will run a simulation on the output of theXi

Strany 50 - Up Sample

Using an EDIF software flow 143Using the Xilinx Softwarewere generated in Simulink. Provided that your design was error free, the ModelSimconsole wind

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144 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideXilinx supplies two sets of instructions for compiling your IP libraries usin

Strany 52 - Communication

Xilinx software tools resources 145Using the Xilinx SoftwareAfter you make this association, your System Generator projects within ProjectNavigator wi

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146 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideChapter 6Auxiliary FilesDemonstration designsSeveral demonstration designs ha

Strany 54 - Depuncture

Perl scripts 147Auxiliary FilesYou can also launch the MATLAB Demos window from the MATLAB console bytyping:>> demoPerl scriptsAs a convenience,

Strany 55 - Interleaver Deinterleaver

148 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide

Strany 56

What is a Xilinx Block? 15Xilinx Blockset OverviewChapter 2Xilinx Blockset OverviewThis chapter gives an overview of the Xilinx Blockset, including ba

Strany 57

16 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideportion of a Simulink model to be implemented in an FPGA must be built exclusi

Strany 58 - Puncture

The Nature of Signals in the Xilinx Blockset 17Xilinx Blockset OverviewAs an example, the figures shown below depict the Xilinx Negate block parameters

Strany 59 - RS Decoder

18 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideUse of Xilinx Smart-IP Cores by the System GeneratorTo increase hardware perfo

Strany 60

Common Options in Block Parameters Dialog Box 19Xilinx Blockset OverviewXilinx LogiCORE VersionsThe Xilinx LogiCORE blocks (indicating the version n

Strany 61

2 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideAbout This ManualThis document is a reference guide for system designers who ar

Strany 62

20 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidespecific parameters are described in the specific block documentation in the nex

Strany 63 - RS Encoder

Common Options in Block Parameters Dialog Box 21Xilinx Blockset OverviewPrecisionThe fundamental computational mode in the Xilinx Blockset is arbitrar

Strany 64

22 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideIn the Simulink environment, the Override with Doubles option allows you tosim

Strany 65

Basic Elements 23Xilinx BlocksChapter 3Xilinx BlocksThis chapter describes each Xilinx block in detail. Xilinx blocks are grouped within sixcategories

Strany 66

24 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 67

Basic Elements 25Xilinx BlocksThe wrapper file is named to match the top level VHDL file generated for yourproject. For example, if your top level file i

Strany 68 - Viterbi Decoder

26 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideAddressable Shift RegisterThe Xilinx Addressable Shift Register block is a var

Strany 69

Basic Elements 27Xilinx BlocksBlock Parameters Dialog BoxThe Addressable Shift Register Block Parameters Dialog Box can be invoked bydouble-clicking t

Strany 70 - Xilinx LogiCore

28 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlack BoxThe Xilinx Black Box token enables you to instantiate your ownspecial

Strany 71

Basic Elements 29Xilinx Blocksinfer them in the generated VHDL. The block parameters dialog box can be invokedby double-clicking the icon in your Simu

Strany 72

3Additional ResourcesFor additional information, go to http://support.xilinx.com. The followingtable lists some additional resources.Resource Descript

Strany 73

30 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideinput and output ports respectively. To configure the black box, enter the para

Strany 74

Basic Elements 31Xilinx BlocksConstantThe Xilinx Constant block generates a constant.This block is similar to theSimulink constant block, but can be u

Strany 75 - Xk() xm()W

32 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 76

Basic Elements 33Xilinx BlocksThe block can be configured as a free running up or down counter byselecting the Provide Reset Pin option on the block pa

Strany 77 - Block Timing

34 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe Counter block parameters dialog box is invoked

Strany 78

Basic Elements 35Xilinx BlocksXilinx LogiCOREThe block always uses the Xilinx LogiCORE: Binary Counter V5.0.The Core datasheet can be found on your lo

Strany 79

36 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideDown SampleThe Xilinx Down Sample block reduces the sample rate at the pointwh

Strany 80

Basic Elements 37Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink mo

Strany 81 - Accumulator

38 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideMuxThe Xilinx Mux block implements a multiplexer.The block has one select inpu

Strany 82

Basic Elements 39Xilinx Blocks%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\doc\bus_mux.pdfParallel to SerialThe Parallel to Serial bloc

Strany 83

4 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideConventionsThis document uses the following conventions. An example illustrates

Strany 84

40 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxFigure 3-15: Parallel to Serial block parameters

Strany 85 - Inverter

Basic Elements 41Xilinx BlocksBlock InterfaceThe block has one input port for the data and an optional input reset port. The initialoutput value is sp

Strany 86

42 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideReinterpretThe Reinterpret block forces its output to a new type without anyre

Strany 87

Basic Elements 43Xilinx BlocksBlock Parameters Dialog boxFigure 3-17: Reinterpret block parameters dialog boxParameters specific to the block are:• F

Strany 88

44 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe following waveform illustrates the block’s behavior:Figure 3-18: Example

Strany 89

Basic Elements 45Xilinx Blocks• Binary Point: Output binary point locationOther parameters usedby thisblock areexplained in the CommonParameters secti

Strany 90 - Relational

46 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideonly the first three fractional bits. The following diagram illustrates how to

Strany 91

Basic Elements 47Xilinx BlocksFigure 3-22: Slice block parameters dialog box showing different optionsParameters specific to the block are:• Specify

Strany 92

48 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe following diagram illustrates the operation of this block.Figure 3-23: S

Strany 93 - SineCosine

Basic Elements 49Xilinx BlocksIt is instructive to note that the following model produces behavior identical to theone with the Sync block. This one,

Strany 94

5ContentsChapter 1 IntroductionIndustry and Product Overview ...8System

Strany 95 - Threshold

50 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideadded to the channel that is last to present a valid input sample. Note that i

Strany 96 - MATLAB I/O

Basic Elements 51Xilinx Blocksfrom din to dout. Whenever possible, put a register or delay block after an up sampleblock.Figure 3-28: Example of up

Strany 97 - Gateway In

52 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideCommunicationThe blocks in the Communication library implement functions used

Strany 98

Communication 53Xilinx BlocksBlock Parameters Dialog BoxThe following figure shows the block parameters dialog box.Figure 3-31: Convolutional encoder

Strany 99 - Gateway Out

54 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideDepunctureThe Xilinx Depuncture block allows you to insert arbitrary symbol in

Strany 100

Communication 55Xilinx BlocksBlock Parameters Dialog BoxThe Xilinx depuncture block can be configured using its Block Parameters dialog box.Figure 3-33

Strany 101 - Quantization Error Blocks

56 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideFigure 3-34: Forney convolutional interleaver with a constant differencebetw

Strany 102 - Dual Port RAM

Communication 57Xilinx BlocksWhen the branch lengths are specified as an array, the block operates the same ineither interleaver or deinterleaver mode

Strany 103

58 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe Core datasheet can be found on your local disk at:%XILINX%\coregen\ip\xili

Strany 104 - Block Parameters Dialog Box

Communication 59Xilinx BlocksBlock Parameters Dialog BoxThe Xilinx puncture block can be configured using its Block Parameters dialog box.Figure 3-38:

Strany 105 - Xilinx LogiCORE

6 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideConcat ...

Strany 106

60 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe probability of each of the three outcomes depends on the particular Reed-S

Strany 107

Communication 61Xilinx BlocksBlock Parameters Dialog BoxThe RS Decoder block can be configured using its Block Parameters dialog box.Figure 3-40: Ree

Strany 108

62 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide♦ IESS-308 (208): implements IESS-308 specification (208, 192) shortened RScode

Strany 109

Communication 63Xilinx Blocks• Scaling Factor: Scaling factor for the generator polynomial root index.Normally h is 1; however, it can be any positive

Strany 110 - Single Port RAM

64 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidetype of errors that can be corrected depends on the characteristics of the Ree

Strany 111

Communication 65Xilinx BlocksBlock InterfaceThe Xilinx RS Encoder block has two inputs (din, rst) and three output (dout,info and rfd) ports. The RS E

Strany 112

66 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe RS Encoder block can be configured using its Blo

Strany 113

Communication 67Xilinx Blocks♦ IESS-308 (225): implements IESS-308 specification (225, 205) shortened RScode.• Symbol Width: specifies the symbol width

Strany 114 - State Machine

68 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideOther parameters used by this block aredescribed inthe CommonParameters sectio

Strany 115

Communication 69Xilinx BlocksBlock InterfaceThe Viterbi Decoder has eithertwo or threeinputports and one output port. The decoder can haveeither two o

Strany 116 - Moore State Machine

7Gateway Out...99Quantization Error Blocks ...

Strany 117

70 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• Traceback Length:Length of the traceback throughthe Viterbi trellis.Optimall

Strany 118

DSP 71Xilinx BlocksBlock InterfaceThe CIC Block has one input and one output port. The input port can be between 1and 32 bits (inclusive).The twobasi

Strany 119

72 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe CIC Block can be configured using its Block Para

Strany 120

DSP 73Xilinx BlocksDDSThe Xilinx DDS Block implements a direct digital synthesizer (DDS),also commonly called a numerically controlled oscillator (NCO

Strany 121

74 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 122

DSP 75Xilinx Blocks• Phase Increment Type: specifies ∆θ to be either constant or register. Choiceof register activates optional ports on the block.• P

Strany 123

76 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidefor k=0, 1, ... , N-1, whereis a principal N-th root of unity.The FFT block ac

Strany 124

DSP 77Xilinx Blocks• Memory Usage:number ofmemorybanks usedtocompute thetransform,one ofSingle, Double, Triple (not used for 16 point FFTs).• Scale Ou

Strany 125

78 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideFigure 3-52: FFT Timing CharacteristicsFor 16-point FFTs, the block is alway

Strany 126

DSP 79Xilinx BlocksThe Dual Port Block Memory LogiCORE datasheet can be found on your local disk at:%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkm

Strany 127 - Chapter 4

8 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideChapter 1IntroductionThis chapter describes the basic concepts and tools of the

Strany 128 - Using Black Boxes

80 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 129 - Black Box window

Math 81Xilinx Blocks• Polyphase behavior: Decimation, Interpolation, Single rate.• Latency: specify input sample period latency.• Hardware Over-Sampli

Strany 130

82 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 131

Math 83Xilinx Blocks%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\doc\accum.pdfAddSubThe Xilinx AddSub block implements an adder/subtrac

Strany 132

84 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideuses the Xilinx LogiCORE Adder Subtractor V5.0. Otherwise, the block isimpleme

Strany 133 - Multicycle Path Constraints

Math 85Xilinx Blockssaturated as needed. A positive value is implemented as an unsigned number, anegative value as signed.• Number of Bits in Constant

Strany 134

86 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 135

Math 87Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model.Figure

Strany 136 - Important Issues

88 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideMultThe Xilinx Mult block implements a multiplier. It computes theproduct of t

Strany 137

Math 89Xilinx BlocksFigure 3-60: Mult block parameters dialog box - sequential typeParameters specific to the Mult block are:• Multiplier Type: direc

Strany 138 - System Generator

System Generator 9Introductionconstructs for simulation, its synthesizable subset is far too restrictive for systemdesign.System Generator is a softwa

Strany 139 - Using the Xilinx Software

90 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideNegateThe Xilinx Negate block computes the arithmetic negation (two’scomplemen

Strany 140 - Implementing your design

Math 91Xilinx Blocks♦ equal-to (a = b)♦ not-equal-to (a != b)♦ less-than (a < b)♦ greater-than (a > b)♦ less-than-or-equal-to (a <= b)♦ great

Strany 141

92 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideScaleThe Xilinx Scale block scales its input by a power of two. The powercan b

Strany 142

Math 93Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model.Figure

Strany 143 - Simulation

94 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidefundamental sinusoid lie in the half-open interval [-1, 1]. If you need a bal

Strany 144 - MXE libraries

Math 95Xilinx Blocks64. This corresponds to one CLB per output bit. If the table depth is greater than 64, aquarterwave isstored, andadditional logici

Strany 145

96 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Strany 146 - Auxiliary Files

MATLAB I/O 97Xilinx BlocksLogiCOREs, as well as signals and control circuits to drive the clock network.Consequently, most System Generator blocks do

Strany 147 - Perl scripts

98 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe block parameters dialog box can be invoked by double-clicking the icon in

Strany 148 - 148 Xilinx Development System

MATLAB I/O 99Xilinx BlocksIt should be noted there is a valid bit that accompanies the data signal. It isconstrained at the same rate. For more infor

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