Xilinx LogiCore PLB PCI Full Bridge Uživatelský manuál stáhnout pdf

PLB PCI Full Bridge (v1.00a)

DS508 March 21, 2006

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Product Specification

DS508 March 21, 2006 www.xilinx.com 1

Product Specification

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RLY AC

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Introduction

The PLB PCI Full Bridge design provides full bridge

functionality between the Xilinx 64-bit PLB and a 32-bit

Revision 2.2 compliant Peripheral Component

Interconnect (PCI) bus. The bridge is referred to as the

PLB PCI Bridge in this document.

The Xilinx PLB is a 64-bit bus subset of the IBM PLB

described in the 64-Bit Processor Local Bus Architecture

Specification v3.5. Details on the Xilinx PLB and the PLB

IPIF are found in the Processor IP Reference Guide. This

guide is accessed via EDK help or the Xilinx website at:

http://www.xilinx.com/ise/embedded/proc_ip_ref_

guide.pdf.

The LogiCORE PCI v3.0 core provides an interface with

the PCI bus. Details of the LogiCORE PCI 32 v3.0 core

operation is found in the

Xilinx LogiCORE PCI Interface

v3.0 Product Specification and the Xilinx The Real-PCI

Design Guide v3.0.

Host bridge functionality (often called North bridge

functionality) is an optional functionality.

Configuration Read and Write PCI commands can be

performed from the PLB-side of the bridge. The PLB

PCI Bridge supports a 32-bit/33 MHz PCI bus only.

Exceptions to the support of PCI commands supported

by the v3.0 core are outlined in the

Features section.

The PLB PCI Bridge design has parameters that allow

customers to configure the bridge to suit their

application. The parameterizable features of the design

are discussed in the

Bus Interface Parameters section.

LogiCORE™ Facts

Core Specifics

Supported Device

Family

Virtex™-II Pro, Virtex-4

Version of Core plb_pci v1.00a

Resources Used

Virtex-IIP Min Max

I/O (PCI) 49 50

I/O (PLB-related) 397 433

LUTs 3350 3870

FFs 2570 2970

Block RAMs 8 8

Provided with Core

Documentation Product Specification

Design File Formats VHDL

Constraints File example UCF-file

Verification N/A

Instantiation Template N/A

Reference Designs None

Design Tool Requirements

Xilinx Implementation

Tools

8.1.1i or later

Verification N/A

Simulation ModelSim SE/EE 5.8d or later

Synthesis XST

Support

Support provided by Xilinx, Inc.

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Shrnutí obsahu

Strany 1 - PLB PCI Full Bridge (v1.00a)

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PLB PCI Full Bridge (v1.00a)10 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSG27IPIF BAR to which PCI BAR 0 is mappedC_PCIBAR2

Strany 3 - Product Specification

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 11Product SpecificationEARLY ACCESSG40PCI2IPIF FIFO occupancy level in double words th

Strany 4

PLB PCI Full Bridge (v1.00a)12 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSG50Number of IDELAY controllers instantiated. Ignor

Strany 5 - Bus Interface Parameters

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 13Product SpecificationEARLY ACCESSG61Include configuration functionality via IPIF tra

Strany 6

PLB PCI Full Bridge (v1.00a)14 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSPLB PCI Bus Interface I/O SignalsThe I/O signals fo

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 15Product SpecificationEARLY ACCESSP27 Sl_rdBTerm PLB Bus OP28Sl_MBusy(0:C_PLB_NUM_MAS

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PLB PCI Full Bridge (v1.00a)16 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSP55CBE[(C_PCI_DBUS_WIDTH/8)-1:0]PCI Bus I/O Time-mu

Strany 9

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 17Product SpecificationEARLY ACCESSThe REQ_N_toArb facilitates an interface to an inte

Strany 10 - EARLY ACCESS

PLB PCI Full Bridge (v1.00a)18 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSPort and Parameter DependenciesThe dependencies bet

Strany 11 - (1), (2)

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 19Product SpecificationEARLY ACCESSG12 C_IPIFBAR2PCIBAR_2G1, G10, G11 and G48Meaningfu

Strany 12

PLB PCI Full Bridge (v1.00a)2 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSFeatures• Independent PLB and PCI clocks• 33 MHz, 32

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PLB PCI Full Bridge (v1.00a)20 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSG26 C_PCIBAR_NUM G27-G32The set of PCI/v3.0 BAR-par

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 21Product SpecificationEARLY ACCESSG43C_NUM_PCI_RETRIES_IN_WRITESG44C_NUM_PCI_PRDS_BET

Strany 15

PLB PCI Full Bridge (v1.00a)22 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSSupported PCI Bus CommandsThe list of commands supp

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 23Product SpecificationEARLY ACCESSPLB PCI Bridge Register DescriptionsThe PLB PCI Bri

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PLB PCI Full Bridge (v1.00a)24 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSRegister and Parameter DependenciesThe addressable

Strany 18

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 25Product SpecificationEARLY ACCESSGlobal Interrupt Enable Register DescriptionA globa

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PLB PCI Full Bridge (v1.00a)26 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSBridge Interrupt Enable Register DescriptionThe PLB

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 27Product SpecificationEARLY ACCESSPLB PCI Bridge Reset Register DescriptionThe IP Res

Strany 21

PLB PCI Full Bridge (v1.00a)28 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSConfiguration Address Port Register DescriptionThe

Strany 22

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 29Product SpecificationEARLY ACCESSbus number. The highest subordinate bus number is a

Strany 23

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 3Product SpecificationEARLY ACCESSdefault in all transfers. Address translation is per

Strany 24

PLB PCI Full Bridge (v1.00a)30 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSThe example below shows how the IPIFBAR2PCIBAR_N re

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 31Product SpecificationEARLY ACCESSWriting 0xFEDC0000 to IPIFBAR2PCIBAR_1 High-Order B

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PLB PCI Full Bridge (v1.00a)32 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSPLB PCI TransactionsThe following subsections discu

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 33Product SpecificationEARLY ACCESSFor all the transactions listed above, the followin

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PLB PCI Full Bridge (v1.00a)34 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESS• Address translations in both directions are perfo

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 35Product SpecificationEARLY ACCESSmode). • If the PCI target address space is IO-spac

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PLB PCI Full Bridge (v1.00a)36 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESS• If a SERR occurs during a valid data phase on a b

Strany 31

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 37Product SpecificationEARLY ACCESSTable 17 summarizes the abnormal conditions with wh

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PLB PCI Full Bridge (v1.00a)38 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSwhen an incomplete PCI transactions occur or when P

Strany 33

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 39Product SpecificationEARLY ACCESSburst write data from the PLB to PCI beyond the val

Strany 34

PLB PCI Full Bridge (v1.00a)4 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSSystem ResetWhen the bridge is reset, both RST_N and

Strany 35

PLB PCI Full Bridge (v1.00a)40 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESStransaction. The PLB PCI Bridge performs retries up

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 41Product SpecificationEARLY ACCESSPCI Initiator Initiates a Read Request of a PLB Sla

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PLB PCI Full Bridge (v1.00a)42 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSFurthermore, it is the responsibility of the PCI in

Strany 38

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 43Product SpecificationEARLY ACCESSIf the PLB clock is slower, the data flow is a seri

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Ta bl e 1 9 : Response to PCI initiator doing a read of a remote PLB slave that terminates the transfer with an abnormal condition on PLB bus Abno

Strany 40

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 45Product SpecificationEARLY ACCESSnumber of double words are written, the IPIF master

Strany 41

PLB PCI Full Bridge (v1.00a)46 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSdefined number of retries are not successful, the P

Strany 42

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 47Product SpecificationEARLY ACCESSbridge is not used. As with Memory and IO data tran

Strany 43

Table 21: Results of v3.0 core Command Register configuration by remote host bridge (PCI-side) and by self-configuration (PLB-side)Results in Comman

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 49Product SpecificationEARLY ACCESSto the Configuration Data Port register initiates a

Strany 45

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 5Product SpecificationEARLY ACCESScore. These documents detail the v3.0 core operation

Strany 46

PLB PCI Full Bridge (v1.00a)50 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSsubordinate buses. Device numbers are independent f

Strany 47 - Configuration Space Header

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 51Product SpecificationEARLY ACCESSDesign DebugThe OBP PCI Bridge has a test vector ou

Strany 48

PLB PCI Full Bridge (v1.00a)52 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSThe constraints are also implemented automatically

Strany 49

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 53Product SpecificationEARLY ACCESSNET "*/RST_N" IOBDELAY = BOTH ;NET &q

Strany 50

PLB PCI Full Bridge (v1.00a)54 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESS#TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.000 A

Strany 51 - Design Contraints

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 55Product SpecificationEARLY ACCESSone IDELAYCTRl without LOC constraints, the tools w

Strany 52

PLB PCI Full Bridge (v1.00a)56 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSThe parameter C_IDELAYCTRL_LOC has the syntax of ID

Strany 53

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 57Product SpecificationEARLY ACCESSthe ucf-file in the implementation directory of the

Strany 54

PLB PCI Full Bridge (v1.00a)58 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSReference DocumentsThe following documents contain

Strany 55

PLB PCI Full Bridge (v1.00a)6 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSExample 3 outlines the use of the PCIBAR parameter s

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PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 7Product SpecificationEARLY ACCESSAs in example 1, it is assumed that the parameter C_

Strany 57

PLB PCI Full Bridge (v1.00a)8 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSAccessing the PLB PCI Bridge PCIBAR_1 with address 0

Strany 58

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 9Product SpecificationEARLY ACCESSG13IPIF BAR 2 memory designatorC_IPIF_SPACETYPE_20 =

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