Xilinx Spartan-3E 1600E manuály

Xilinx Spartan-3E 1600E Uživatelský manuál (168 strany)

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MicroBlaze Development

1

Kit Spartan-3E 1600E

1

Edition User Guide

1

Revision History

2

Table of Contents

3

Chapter 6: VGA Display Port

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Chapter 12: SPI Serial Flash

5

Chapter 13: DDR SDRAM

6

Appendix A: Schematics

7

About This Guide

9

Additional Resources

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Introduction and Overview

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Key Components and Features

12

Design Trade-Offs

13

UG257_02_01_061306

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Push-Button Switches

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Rotary Push-Button Switch

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Rotary Shaft Encoder

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Discrete LEDs

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Clock Sources

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±2500 Hz or ±50 ppm

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Chapter 3: Clock Sources

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FPGA Configuration Options

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Spartan-3E

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Development Board

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Configuration Mode Jumpers

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PROG Push Button

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DONE Pin LED

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Connecting the USB Cable

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UG257_04_05_061206

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UG257_04_06_0612

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UG257 04-07 06906

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UG257_04_08_061206

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UG257_09_061206

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UG257_04_10_061206

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UG257_04_11_061206

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Generating the PROM File

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UG257_04_12_022706

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UG257_04_13_061206

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UG257_04_14_061206

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UG257_04_15_061206

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UG257_4-16_061206

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UG257_4-17_061206

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UG257_4-18_060906

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UG257_4-19_061206

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UG257_4-20_061206

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UG257 4 21 061206

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UG257_04_22_061206

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UG257_4-23_060106

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UG257_4-24_061

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UG257_04_25_061206

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UG257_04_26_061206

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Character LCD Screen

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Voltage Compatibility

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LCD Controller

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UG257_05_04_061206

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Command Set

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Disabled

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Clear Display

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Return Cursor Home

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Entry Mode Set

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Display On/Off

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Cursor and Display Shift

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Function Set

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Set CG RAM Address

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Set DD RAM Address

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Read Busy Flag and Address

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Operation

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Power-On Initialization

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Display Configuration

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VGA Display Port

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UG257_06_02_06050

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VGA Signal Timing

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Chapter 6: VGA Display Port

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RS-232 Serial Ports

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UG257_07_01_060506

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PS/2 Mouse/Keyboard Port

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Keyboard

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Caps L o c k

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Back Space

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Mouse Arrow

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U257_08_06_060506

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Chapter 9

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Interface Signals

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SPI Communication Details

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Communication Protocol

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DAC Outputs A and B

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Analog Capture Circuit

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UG257_10_02_060706

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Programmable Pre-Amplifier

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SPI Control Interface

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Interface

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UG257_10_08_061406

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Chapter 11

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StrataFlash Connections

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Shared Connections

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SPI Serial Flash

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Configuring from SPI Flash

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UG257_12_04_061506

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UG257_12_05_060806

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UG257_12_06_060806

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UG257_12_07_060806

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UG257_12_08_060806

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UG257_12_09_060806

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UG257_12_10_060806

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UG257_12_11_060806

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UG257_12-12_062606

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UG257_12_1

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3_060806

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UG257_12_14_060806

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with Flying Leads

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UG257_12_15_060806

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NO JUMPER

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Additional Design Details

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°. The 16-pin SOIC

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UG257_12_19_060806

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Related Resources

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DDR SDRAM

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DDR SDRAM Connections

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UCF Location Constraints

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Chapter 13: DDR SDRAM

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Chapter 14

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Ethernet PHY Connections

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UG257_14_03_060806

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Expansion Connectors

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Hirose 100-pin Expansion

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Connector (J3)

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Spartan-3E FPGA

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Compatible Board

120

Mating Receptacle Connectors

120

Differential I/O

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Using Differential Inputs

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Using Differential Outputs

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Six-Pin Accessory Headers

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XC2C64A CoolRunner-II CPLD

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FPGA Connections to CPLD

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DS2432 1-Wire SHA-1 EEPROM

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Appendix A

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Schematics

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UG257_A01_060606

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UG257_A02_060606

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Appendix A: Schematics

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UG257_A03_060606

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Voltage Regulators

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Flash, JTAG Connections

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UG257_A05_060606

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UG257_A06_060606

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FPGA I/O Banks 2 and 3

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Power Supply Decoupling

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UG257_A10_060606

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UG257_A11_060606

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UG257_A12_060606

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Termination

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UG257_A13_060606

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Appendix B

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